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gl 811e usb 2.0 to ata / atapi bridge controller datasheet revision 1. 2 2 dec . 2 9 , 200 4 g enesys l ogic , i nc .
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 2 copyright: copyright ? 200 4 genesys l ogic incorporated. all rights reserved. no part of the materials may be reproduced in any form or by a ny means without prior written consent of genesys l ogic inc.. disclaimer : all materials are provided "as is" without express or implied warranty of any kind. no license or right is granted under any patent or trademark of genesys logic inc.. genesys log ic hereby disclaims all warranties and conditions in regard to materials, including all warranties, implied or express, of merchantability, fitness for any particular purpose, and non - infringement of intellectual property. in no event shall genesys logic be liable for any damages including, without limitation, damages resulting from loss of information or profits. please be advised that the materials may contain errors or ommisions. genesys logic may make changes to the materials or to the products descr ibed therein at any time without notice. trademarks: is a registrated trademark of genesys l ogic inc.. all trademarks are the properties of their respective owners. office: genesys logic, inc. 12f, no. 205, sec. 3, beish i n rd., shindian city, taip ei, taiwan tel: (886 - 2) 8913 - 1888 fax: (886 - 2) 6629 - 6168 http://www.genesyslogic.com
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 3 revision history revision date d escription 1.00 06/13/2003 first formal release. 1.01 06/24/2003 changed produc t name from gl811 to GL811E. 1.10 11/26/2003 1. added some features in chapter 2. 2. added 64 pin lqfp data in pinouts, pin description and package dimension. 3. added chapter 8 ? ordering infromation ? . 1.11 11/27/2003 changed pin# 38,39,21 name from ioad r0~2 to da0~2. 1.20 05/05/2004 1. removed pio mode description. 2. changed package dimension 1.21 09/23/2004 1. added usb2.0 certified test id in chapter 2 features 2. updated ic marking in package dimension diagram 1.2 2 12 /2 9 /2004 added tqfp package in formation in features, package dimension and ordering information.
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 4 table of contents chapter 1 general d escription ................................ ................................ ........... 7 chapter 2 features ................................ ................................ ................................ ....... 8 chapter 3 pin assig nment ................................ ................................ ......................... 9 3.1 p inouts ................................ ................................ ................................ ............................... 9 3. 2 p in d escriptions ................................ ................................ ................................ ............ 11 chapter 4 block dia gram ................................ ................................ ...................... 13 chapter 5 function description ................................ ................................ ....... 14 chapter 6 electrica l characteristics ................................ ...................... 15 6.1 a bsolute m aximum r atings ................................ ................................ ...................... 15 6.2 t emperature c onditions ................................ ................................ ........................... 15 6.3 dc c haracteristics ................................ ................................ ................................ .... 15 6.3.1 i/o 8 type digital pins (for pad type i/o 8 @ v cc =3.6v) ............................... 15 6.3.2 i/o 16 type digital pins (for pad type i/o 16 @ v cc =3.6v) ........................... 16 6.3.3 d+/ d - (for pad type u20mia @ v cc =3.6v) ................................ ....................... 16 6.3.4 swi tching characteristics ................................ ................................ ...................... 16 6.4 ac c haracteristics - ata/ atapi ................................ ................................ ........... 17 6.4.1 register transfers ................................ ................................ ................................ .. 18 6.4.2 multiword dma data transfer ................................ ................................ ............. 19 6.4.3 ultra dma data transfer ................................ ................................ ....................... 23 6.5 ac c haracteristics - usb 2.0 ................................ ................................ ................... 30 chapter 7 package d imension ................................ ................................ ............. 31 chapter 8 ordering information ................................ ................................ .... 35
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 5 list of figures f igure 3.1 - 48 p in lqfp/tqfp p inout d iagram ................................ .......................... 9 f igure 3.2 - 64 p in lqfp/tqfp p inout d iagram ................................ ........................ 10 f igure 4.1 - b lock d iagram ................................ ................................ ............................. 13 f igure 6.1 - i nitiating a m ultiword dma d ata b urst ................................ ........... 20 f igure 6.2 - s ustaining a m ultiword dma d ata b urst ................................ .......... 21 f igure 6.3 - d evice t erminating a m ultiword dma d ata b urst ........................ 21 f igure 6.4 - h o st terminating a m ultiword dma d ata b urst ............................ 22 f igure 6.5 - i nitiating an u ltra dma d ata - i n b urst ................................ .............. 24 f igure 6.6 - s ustained u ltra dma d ata - i n b urst ................................ .................... 24 f igure 6.7 - h ost p ausing an u ltra dma d ata - i n b urst ................................ ........ 25 f igure 6.8 - d evice t erminating an u ltra dma d ata - i n b urst .......................... 25 f igure 6.9 - h ost t erminating an u ltra dma d ata - i n b urst .............................. 26 f igure 6.10 - i nitiating an u ltra dma d ata - o ut b urst ................................ ........ 27 f igure 6.11 - s ustained u ltra dma d ata - o ut b urst ................................ .............. 27 f igure 6.12 - d evice p ausing an u ltra dma d ata - o ut b urst .............................. 28 f igure 6.13 - h ost terminating an u ltra dma data - out burst ........................... 29 f igure 6.14 - d evice t erminating an u ltra dma d ata - o ut b urst ..................... 30 f igure 7.1 - GL811E 48 p in lqfp p ackage ................................ ................................ ... 31 f igure 7. 2 - GL811E 48 p in t qfp p ackage ................................ ................................ ... 32 f igure 7. 3 - GL811E 64 p in lqfp p ackage ................................ ................................ ... 33 f igure 7. 4 - GL811E 64 p in t qfp p ackage ................................ ................................ ... 34
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 6 list of tables t able 3.1 - p in d escriptions ................................ ................................ ............................. 11 t able 6.1 - m aximum r atings ................................ ................................ .......................... 15 t able 6.2 - t emperature c onditions ................................ ................................ ............ 15 t able 6.3 - i/o 8 t ype digital pins (f or pad type i/o 8 @ v cc =3.6v) ..................... 15 t able 6.4 - i/o 16 t ype digital pins (f or pad type i/o 16 @ v cc =3.6v) ................. 16 t able 6.5 - d+/ d - (f or pad type u 20 mia @ v cc =3.6v) ................................ ................ 16 t able 6.6 - s witching c haracteristics ................................ ................................ ....... 16 t able 6.7 - u ltra dma data burst timing r equirements ................................ ....... 2 3 t able 8.1 - o rdering i nformation ................................ ................................ ................. 35
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 7 chapter 1 genera l description the gl811 e is a highly - compatible, low cost usb 2.0 to ata / atapi bridge controller , which integrates genesys logic own design high speed utmi (usb 2.0 transceiver macrocell interface) transceiver. as a one - chip solution which complies wit h universal serial bus s pecification r ev. 2.0 and ata / atapi - 6 s pecification r ev 1.0, the gl811 e can support various kinds of ata / atapi device. there are totally 4 endpoints in the gl811 e controller, control (0), bulk in (1), bulk out (2), and interrupt (3). by complies with the usb storage class specification ver.1.0 (bulk only protocol) , the GL811E can support not only plug and play but also windows xp/ 2000/ me default driver. the gl811 e uses 12mhz crystal and slew - rate controlled pads to reduce the emi issue. with 48 - pin lqfp (9mmx9mm) package , the gl811 e is the best cost/ performance solution to fit different situations in the usb 2.0 high speed storage class applications such a s hard disk, cd - rom, cd - r / rw and dvd - rom.
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 8 chapter 2 f eatures complies with universal serial bus s pecification r ev. 2.0. complies with ata/atapi - 6 s pecification r ev 1.0. complies with usb storage class specification ver.1.0. (bulk only protocol) operating system supported: win xp / 2000 / me / 98 / 98se; mac os 9.x / x. integrated usb 2.0 transceiver macrocell interface (utmi) transceiver and serial interface engine (sie). usb 2.0 certified (testid= 40380268 ) supports 4 endpoints: control (0) / bulk read (1) / bulk write (2) / interrupt (3). 64 / 5 12 bytes data payload for full / high speed bulk endpoint. supports 16 - bit m ultiword dma mode and ultra dma mode interface (ultra 33 / 66). embed ded 7.5 mips risc cpu . rom size: 4k words ; ram size: 128 bytes . supports power down mode and usb suspend indica tor. support s usb 2.0 t est mode features . supports 2 gpio (gpio5 & 6) for programmable ap (only for 64 pin package) . supports device power control for power on/off when running suspend mode (only for 64 pin package). supports 32 bit and 48 bit lba hard dis k. provides led indicator for full speed and high speed (only for 64 pin package) . 12 mhz external clock to provide better emi. 3.3v power input; 5v tolerance pad for ide interface . supports wakeup ability. available in 48 - pin lqfp /tqfp and 64 - pin lqfp /tqf p package .
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 9 chapter 3 pin assignment 3.1 pinouts GL811E lqfp/tqfp - 48 gpio7 1 iodd[8] 2 iodd[9] 3 iodd[10] 4 iodd[11] 5 dvcc1 6 dgnd1 7 iodd[12] 8 iodd[13] 9 iodd[14] 10 iodd[15] 11 cblid_ 12 diow_ dior_ iordy dmack_ intrq da1 da0 cs0_ test agnd1 x1 x2 36 35 34 33 32 31 30 29 28 27 26 25 dmarq 37 iodd[0] 38 iodd[1] 39 iodd[2] 40 iodd[3] 41 dgnd2 42 dvcc2 43 iodd[4] 44 iodd[5] 45 iodd[6] 46 iodd[7] 47 gpio1 48 avcc1 rref agnd0 dmh dmf dph dpf avcc0 rpu reset# da2/sk cs1_ 24 23 22 21 20 19 18 17 16 15 14 13 figure 3.1 - 48 pin lqfp /tqfp pinout diagram
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 10 GL811E lqfp/tqfp - 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 gpio7 nc gpio5 gpio6 iodd8 iodd9 iodd10 iodd11 dvcc2 dgnd2 iodd12 iodd13 iodd14 iodd15 cblid_ nc 1 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 diow_ dior_ iordy dmack_ intrq nc nc nc nc da1 da0 cs0 nc nc agnd1 x1 x2 avcc1 rref agnd0 dmh dmf dph dpf avcc0 rpu reset# da2 cs1_ nc nc nc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 nc dmarq iodd0 iodd1 iodd2 iodd3 dgnd1 dvcc1 iodd4 iodd5 iodd6 iodd7 gpio1 pwr_ctl f_led h_led 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 49 figure 3.2 - 64 pin lqfp /tqfp pinout diagram
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 11 3.2 pin d escriptions table 3.1 - pin descriptions pin name 48pin# 64 pin# i/o type d escription gpio 7 1 1 b (tri) g p io 7 (**) gpio5~6 - 3,4 o ap programmable iodd[8:11] 2~5 5~8 b (tri) ide data bus 8~11 dvcc1 ~2 6 ,43 56,9 p digital vcc dgnd1 ~2 7 ,42 55,10 p digital ground i o dd[12: 15] 8~11 11~14 b (tri) ide data bus 12~15 cblid_ 12 15 i (tri) cable select input cs1_ 13 20 o (tri) chip select 1 da2 /sk 14 - o (tri) ide address 2 / serial data clock for eeprom reset# 15 22 i (pu) reset pin (* * *) rpu 16 23 a 3.3v output avcc0 ~1 17 ,24 24,31 p analog vcc dpf 18 25 b full speed dp dph 19 26 b high speed dp dmf 20 27 b full speed dm dmh 21 28 b high speed dm agnd0 ~1 22 ,27 29,34 p analog ground rref 23 30 a reference resister connect (* ** *) x2 25 32 b crystal output x1 26 33 i c rystal input, 12mhz test 28 - i (pd) test mode input cs0_ 29 37 o (tri) chip select 0 da0 ~1 30 ,31 38,39 o (tri) ide address 0 ~1 da 2 - 21 o (tri) ide address 2 intrq 32 44 i (tri) ide interrupt input dmack_ 33 45 o (tri) ide acknowledge iordy 34 46 i (pu) ide ready
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 12 dior_ 35 47 o (tri) ide read signal diow_ 36 48 o (tri) ide write signal dmarq 37 50 i (pd) ide request i o dd[0:3] 38~41 51~54 b (tri) ide data bus 0~3 i o dd[4:7] 44~47 57~60 b (tri) ide data bus 4~7 gpio1 48 61 b (tri) gpio1 pwr_ctl - 62 o power control f_led - 63 o full speed led h_led - 64 o high speed led nc - 2,16~19, 35, 49, - no connection (*) the different of i/o 8 type from i/o 16 type is the typical drive current. the typical drive current of i/o 8 type is 8 ma, and for i/ o pad 16 is 16 ma. (**) when operating in default mode: gpio7 is the ata/ atapi reset input, (** * ) when reset pin is pulled low, the ide bus will be in tri - state. (* ** *) rref must be connected with a 510 ohm resister to ground. notation : type o outpu t i input b bi - directional b/i bi - directional, default input b/o bi - directional, default output p power / ground a analog so automatic output low when suspend pu internal pull up pd internal pull down odpu open drain with int ernal pull up tri tri - state
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 13 chapter 4 block diagram figure 4.1 - block diagram cpu control fifo rxfifo1 sie control register utmi logic usb2.0 txcvr clkgen txfifo0 txfifo1 clk30 rxsts txctl data 16 clk15 8 rpu dpf dph dmh dmf rref iodd15 - 0 dmack_ dior_ diow_ cs1_, cs0_ da2 da1 da0 12 mhz 4 intrq cblid_ dmarq iordy x40 x10 rxfifo0 gpio1 gpio7 8/16 - bit ide engine 12 - 96 mhz
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 14 chapter 5 function description 1. usb 2.0 txcvr the usb 2.0 transceiver is t he analog circuitry to handle the usb hs/fs signaling . 2 . utmi (usb 2.0 transceiver macrocell interface) logic the utmi logic is compliant to intel?s utmi specification 1.01. this block handles the low level usb protocol and signaling. the major jobs of utmi logic is data and clock recovery, nrzi encoding/d ecoding, bit stuffing/de - stuffing, usb2.0 test modes supporting and serial / parallel conversion. 3. sie ( s erial i nterface e ngine ) the sie contains the usb packet id and address recognition logic, and other sequencing and state machine logic to handle usb packets and transactions. 4 . pll 10xpll provides the 120mhz clock output for utmi logic block. utmi operates in 120mhz for usb hs data processing. 40xpll block will provide 480mhz for usb hs data transmission. 5. clkgen clkgen is the clock generator blo ck for the logic blocks. it generates 15mhz clock for micro controller, 48mhz for mdma mode, 96mhz for udma mode, and 30mhz clock for utmi, sie, and fifo. 6 . cpu the cpu is the control center of gl811 e . it?s a n 8 - bit micro controller operating in 15mhz, 7 . 5 mips. after receiving a usb command, it decodes the host command, then it re - assigns tasks to the ide engine, gpio, fifo, and response proper data/status to usb host. 7 . ide engine the ide engine is extended from standard ata / atapi protocol. it suppo rts multiword dma mode, and ultra dma mode data transfers. 8 . fifos control fifo is used as control read / write fifo. txfifo0 / txfifo1 are two sets of 512 - byte ping - pong fifo for bulk read endpoint. it buffers data from ide engine, and re - direct to usb sie logic. rxfifo0 / rxfifo1 are two sets of 512 - byte ping - pong fifo for bulk write endpoint. it buffers data from usb sie logic, and re - direct to ide engine. 9 . control registers control register configures gl811 e to proper operation. for example, cpu ca n set register to generate wakeup event, enter suspend, transmits proper usb packet to host. 10 . ata/atapi the GL811E complies with ata/atapi - 6 s pecification r ev . 1 . 0 . please refer to the specification s for more information. 11 . usb 2.0 the GL811E compli es with universal serial bus specification rev. 2.0, and it integrates genesys logic own design utmi transceiver that fully complies with the usb 2.0 transceiver macercell interface (utmi) specification rev. 1.01. please refer to the specification s for mor e information.
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 15 chapter 6 electrical characteristics 6.1 absolute maximum ratings table 6.1 - maximum ratings symbol parameter min. max. unit v cc dc supply voltage +3.0 +3.6 v v i dc input voltage - 0. 3 v cc + 0. 3 v v i/o dc input voltage range for i/o - 0. 3 v cc + 0. 3 v v ai/o dc input voltage for usb d+/d - pins - 0. 3 v cc + 0. 3 v v esd static discharge voltage 4000 v t a ambient temperature 0 100 o c 6.2 temperature conditions table 6.2 - temperature conditions item value storage temperature - 50 o c ~ 1 50 o c operating temperature 0 o c ~ 70 o c 6.3 dc c haracteristics 6.3.1 i/o 8 type digital pins (for pad type i/o 8 @ v cc =3.6v) table 6.3 - i/o 8 type digital pins (for pad type i/o 8 @ v cc =3.6v) parameter min. typ. max. unit current sink @ v ol = 0.4v 7 .79 10.83 14.09 ma current output @ v oh = 2.4v (ttl high) 16.36 19.87 23.39 ma falling slew rate at 30 pf loading capacitance 0.26 0.50 0.80 v/ns rising slew rate at 30 pf loading capacitance 0.30 0.57 0.91 v/ns input high threshold voltage 1.64 v input low threshold voltage 1.36 v hysteresis voltage - 0 - v leakage current for pads with internal pull up or pull down resistor 46 m a pad internal pull down resister 51k 105k 152k ohms pad internal pull up resister 85k 1 68 k 251k ohms supply current 109 ma
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 16 6.3.2 i/o 16 type digital pins (for pad type i/o 16 @ v cc =3.6v) table 6.4 - i/o 16 type digital pins (for pad type i/o 16 @ v cc =3.6v) parameter min. typ. max. unit current sink @ v ol = 0.4v 16.20 21.90 27.68 ma current o utput @ v oh = 2.4v (ttl high) 24.13 29.46 34.80 ma falling slew rate at 30 pf loading capacitance 0.51 0.93 1.35 v/ns rising slew rate at 30 pf loading capacitance 0.46 0.83 1.27 v/ns input high threshold voltage 2.15 v input low threshold volta ge 0.89 v pad internal pull down resister 51k 105k 152k ohms 6.3.3 d+/ d - (for pad type u20mia @ v cc =3.6v) table 6.5 - d+/ d - (for pad type u20mia @ v cc =3.6v) parameter min. typ. max. unit d+/d - static output low (r l of 1.5k to v cc ) 0 0.3 v d +/d - static output high (r l of 15k to gnd ) 2.8 3.6 v differential input sensitivity 0.2 v single - ended receiver threshold 0. 8 2.0 v transceiver capacitance 20 pf hi - z state data line leakage - 10 +10 m a driver output resistance 28 43 ohms 6.3.4 switching characteristics table 6.6 - switching characteristics parameter min. typ. max. unit x1 crystal frequency 11.97 12 12.03 mhz x1 cycle time 83.3 ns d+/d - rise time with 50pf loading 4 20 ns d+/d - fall time with 50pf loading 4 2 0 ns
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 17 6.4 ac characteristics - ata/ atapi the GL811E complies with ata / atapi - 6 s pecification r ev 1.0 , which supports following data transfer modes : 1. dma (direct memory access) data transfer: dma data transfer means of data transfer between device and h ost memory without host processor intervention. - multiword dma: multiword dma is a data transfer protocol used with the read dma, write dma, read dma queued, write dma queued and packet commands. when a multiword dma transfer is enabled as indicated by ide ntify device or identify packet device data, this data transfer protocol shall be used for the data transfers associated with these commends. (please refer to the ata / atapi - 6 s pecification r ev 1.0 for more information. ) - ultra dma: ultra dma i s a data tra nsfer protocol used with the read dma, write dma, read dma queued, write dma queued and packet commands. when this protocol is enabled, the ultra dma protocol shall be used instead of the multiword dma protocol when these commands are issued by the host. t his protocol applies to the ultra dma data burst only. (please refer to the ata / atapi - 6 s pecification r ev 1.0 for more information. ) following listed the symbols and their respective definitions that are used in the timing diagram: all signals are s hown with the asserted condition facing to the top of the page. the negated condition is shown towards the bottom of the page relative to the asserted condition. the interface uses a mixture of negative and positive signals for control and data. the terms asserted and negated are used for consistency and are independent of electrical characteristics. in all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. the following illustrates the representation of a signal named test going from negated to asserted and back to negated, based on the polarity of the signal. - signal transition (asserted or negated) - data transition (asserted or negated) - data valid - undefined but not necessarily released - asserted, negated or released - released - the ? other ? condition if a signal is shown with no ch ange
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 18 6.4.1 register transfers notes: 1. device address consists of signals cs0_, cs1_ and da(2:0). 2. data consists of iodd(7:0). 3. the negation of iordy by the device is used to extend the register transfer cycle. the determination of whether the cycle is to be extended is made by the host after t a from the assertion of dior_ or diow_. the assertion and negation of iordy are described as following: 3.1 device nev er negates iordy, devices keeps iordy released: no wait is generated. 3.2 device negates iordy before t a , but causes iordy to be asserted before t a . iordy is released prior to negation and may be asserted for no more than 5 ns before release: no wait generate d. 3.3 device negates iordy before t a , iordy is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. the cycle completes after iordy is released. for cycles where a wait is generated and dior_ is asserted, the de vice shall read data on iodd(0:7) for t rd before asserting iordy. 4. dmack_ shall remain negated during a register transfer.
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 19 register transfer timing parameters timing (ns) t 0 cycle time 2000 t 1 address valid to dior_/ diow_ setup 1000 t 2 dior_/ diow_ pulse width 8 - bit 300 t 2i dior_/ diow_ recovery time 900 t 3 diow_ data setup 80 t 4 diow_ data hold 40 t 5 dior_ data setup - t 6 dior_ data hold - t 6z dior_ data tristate - t 9 dior_/ diow_ to address valid hold 900 t rd read data valid to iord y active (if iordy initially low after t a ) t a iordy setup time - t b iordy pulse width - t c iordy assertion to release (max) - 6.4.2 multiword dma data transfer register transfer timing parameters timing (ns) t 0 cycle time 120 t d dior_/ diow_ ass erted pulse width 80 t e dior_ data access - t f dior_ data hold - t g dior_/ diow_ data setup 40 t h diow_ data hold 18 t i dmack to dior_/ diow_ setup 18 t j dior_/ diow_ to dmack hold 20 t kr dior_ negated pulse width 36 t kw diow_ negated pulse width 36 t lr dior_ to dmarq delay - t lw diow_ to dmarq delay - t m cs(1:0) (max) valid to dior_/ diow_ 36 t n cs(1:0) hold 18 t z dmack_ to read data released -
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 20 note: the host shall not assert dmack_ or negate both cs0_ and cs1_ until the asse rtion of dmarq is detected. the maximum time from the assertion of dmarq to the assertion of dmack_ or the negation of both cs0_ and cs1_ is not defined. figure 6.1 - initiating a multiword dma d ata b urst
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 21 figure 6.2 - sustaining a multiword dma d ata b urst note: to terminate the data burst, the device shall negate dmarq within the t l of the assertion of the current dior_ or diow_ pulse. the last data word for the burst shall then be transferred by the negation of the current dior_ or diow_ pulse. if all data for the command has not been transferred, the device shall reassert dmarq again at any later time to resume the dma operation. figure 6.3 - device t erminating a multiword dma d ata b urst
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 22 note: 1. to terminate the transmission of a data bu rst, the host shall negate dmack_ within the specified time after a dior_ or diow_ pulse. no further dior_ or diow_ pulses shall be asserted for this burst. 2. if the device is able to continue the transfer of data, the device may leave dmarq asserted and wait for the host to reassert dmack_ or may negate dmarq at any time after detecting that dmack_ has been negated. figure 6.4 - host terminating a multiword dma d ata b urst
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 23 6.4.3 ultra dma data transfer table 6.7 - ultra dma data burst timing requirements mode 0 (in ns) mode 1 (in ns) mode 2 (in ns) mode 3 (in ns) mode 4 (in ns) name min max min max min max min max min max comment t 2cyctyp 240 160 120 90 60 typical sustained average two cycle time t cyc 112 73 54 39 25 cycle tim e allowing for asymmetry and clock variations t 2cyc 230 154 115 86 57 two cycle time allowing for clock variations t ds 15 10 7 7 5 data setup time at recipient t dh 5 5 5 5 5 data hold time at recipient t dvs 70 48 30 20 6 data vali d setup time at sender t dvh 6 6 6 6 6 data valid hold time at sender t fs 0 230 0 200 0 170 0 130 0 120 first storbe time t li 0 150 0 150 0 150 0 100 0 100 limited interlock time t mli 20 20 20 20 20 interlock time with minimum t ui 0 0 0 0 0 unlimited interlock time t az 10 10 10 10 10 maximum time allowed for output drivers to release t zah 20 20 20 20 20 minimum delay time required for output t zad 0 0 0 0 0 drivers to assert or negate t env 20 70 20 70 20 70 20 55 20 55 envelope time t sr 50 30 20 na na strobe to dmardy_ time t rfs 75 70 60 60 60 ready to final strobe time t rp 160 125 100 100 100 minimum time to assert stop or negate dmarq t iordyz 20 20 20 20 20 maximum time before releasing iordy t ziordy 0 0 0 0 0 minimum time before driving strobe t ack 20 20 20 20 20 setup and hold times for dmack_ t ss 50 50 50 50 50 time from strobe edge to negation of dmarq or assertion of stop
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 24 notes: the definitions for the diow_:stop, d ior_:hdmardy_:hstrobe and iordy:ddmardy_:dstrobe signal lines are not in efficient until dmarq and dmack are asserted. figure 6.5 - initiating an ultra dma d ata - i n b urst notes: iodd(15:0) and dstrobe signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. figure 6.6 - sustained ultra dma d ata - i n b urst
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 25 notes: 1. the h ost may assert stop to request termination of the ultra dma burst no sooner than t rp after hdmardy_ is negated. 2. if the t sr timing is not satisfied, the host may receive zero, one, or two more data words from the device. figure 6.7 - host p ausing an ultr a dma d ata - i n b urst notes: the definitions for the diow_:stop, dior_:hdmardy_:hstrobe and iordy:ddmardy_:dstrobe signal lines are no longer in effect after dmarq and dmack are negated. figure 6.8 - device t erminating an ultra dma d ata - i n b urst
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 26 notes: the definitions for the diow_:stop, dior_:hdmardy_:hstrobe and iordy:ddmardy_:dstrobe signal lines are no longer in effect after dmarq and dmack are negated. figure 6.9 - host t erminating an ultra dma d ata - i n b urst
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 27 notes: the definitions for the diow_:stop, dior_:hdmardy_:hstrobe and iordy:ddmardy_:dstrobe signal lines are not in effect until dmarq and dmack are asserted. figure 6.10 - initiating an ultra dma d ata - o ut b urst notes: iodd(15:0) and hstrobe signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the devicet until some time after they are driven by the host. figure 6.11 - sustained ultra dma d ata - o ut b ur st
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 28 notes: 1. the device may negate dmarq to request termination of the ultra dma burst no sooner than t rp after ddmardy_ is negated. 2. if the t sr timing is not satisfied, the device may receive zero, one, or two more data words from the host. figure 6.1 2 - device p ausing an ultra dma d ata - o ut b urst
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 29 notes: the definitions for the diow_:stop, dior_:hdmardy_:hstrobe and iordy:ddmardy_:dstrobe signal lines are no longer in effect after dmarq and dmack are negated. figure 6.13 - host termi nating an ultra dma data - out burst
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 30 notes: the definitions for the diow_:stop, dior_:hdmardy_:hstrobe and iordy:ddmardy_:dstrobe signal lines are no longer in effect after dmarq and dmack are negated. figure 6.14 - device t erminating an ultra d ma d ata - o ut b urst 6.5 ac characteristics - usb 2.0 the GL811E conforms to all timing diagrams and specifications for universal serial bus s pecification r ev. 2.0. please refer to this specification for more information.
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 31 chapter 7 package dimensio n control dimensions are in millimeters. symbol millimeter inch min. nom. max. max. min. nom. a a1 a2 d e d1 e1 r2 r1 c l l1 s b e aaa bbb ccc ddd d2 e2 tolerances of form and position 9.00 basic 9.00 basic 7.00 basic 7.00 basic 0.354 basic 0.354 basic 0.276 basic 0.276 basic 0.05 1.35 1.40 1.60 0.15 1.45 0 0 11 11 3.5 12 12 7 13 13 0.08 0.08 0.20 0.003 0.003 0.008 0 0 11 11 3.5 12 12 7 13 13 0.063 0.006 0.057 0.055 0.002 0.053 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.50 basic 5.50 basic 5.50 basic 0.020 basic 0.217 basic 0.217 basic 1.00 ref 0.039 ref 0.09 0.45 0.20 0.17 0.60 0.20 0.20 0.75 0.27 0.004 0.018 0.008 0.007 0.024 0.008 0.008 0.030 0.011 0 - 0 2 - 0 3 - 0 1 - notes : 1. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm. 1 24 25 36 37 48 12 13 seating plane e b 4x 4x e e1 e2 a a b d c aaa b a d h bbb ddd m c b a s s d b d1 d2 d d a a2 a1 0.05 s l1 c 0 1 - 0 - c c ccc gage plane r1 r2 0.25mm s l 0 3 - 0 2 - h GL811E aaaaaaagaa ywwxxxxxxxx date code lot code internal no. code no. green package figure 7.1 - GL811E 48 pin lqfp package
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 32 control dimensions are in millimeters. symbol millimeter inch min. nom. max. max. min. nom. a a1 a2 d e d1 e1 r2 r1 c l l1 s b e aaa bbb ccc ddd d2 e2 tolerances of form and position 9.00 basic 9.00 basic 7.00 basic 7.00 basic 0.354 basic 0.354 basic 0.276 basic 0.276 basic 0.05 0.95 1.00 1.20 0.15 1.05 0 0 11 11 3.5 12 12 7 13 13 0.08 0.08 0.20 0.003 0.003 0.008 0 0 11 11 3.5 12 12 7 13 13 0.047 0.006 0.041 0.039 0.002 0.037 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.50 basic 5.50 basic 5.50 basic 0.020 basic 0.217 basic 0.217 basic 1.00 ref 0.039 ref 0.09 0.45 0.20 0.17 0.60 0.20 0.20 0.75 0.27 0.004 0.018 0.008 0.007 0.024 0.008 0.008 0.030 0.011 0 - 0 2 - 0 3 - 0 1 - notes : 1. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm. 1 24 25 36 37 48 12 13 seating plane e b 4x 4x e e1 e2 a a b d c aaa b a d h bbb ddd m c b a s s d b d1 d2 d d a a2 a1 0.05 s l1 c 0 1 - 0 - c c ccc gage plane r1 r2 0.25mm s l 0 3 - 0 2 - h GL811E aaaaaaagaa ywwxxxxxxxx date code lot code internal no. code no. green package figure 7. 2 - GL811E 48 pin t qfp package
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 33 16 control dimensions are in millimeters. symbol millimeter inch min. nom. max. max. min. nom. a a1 a2 d d1 e e1 r2 r1 c l l1 s b e aaa bbb ccc ddd d2 e2 tolerances of form and position 12.00 basic 12.00 basic 10.00 basic 10.00 basic 0.472 basic 0.472 basic 0.393 basic 0.393 basic 0.05 1.35 1.40 1.60 0.15 1.45 0 0 11 11 3.5 12 12 7 13 13 0.08 0.08 0.20 0.003 0.003 0.008 0 0 11 11 3.5 12 12 7 13 13 0.063 0.006 0.057 0.055 0.002 0.053 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.50 basic 7.50 basic 7.50 basic 0.020 basic 0.295 basic 0.295 basic 1.00 ref 0.039 ref 0.09 0.45 0.20 0.17 0.60 0.20 0.20 0.75 0.27 0.004 0.018 0.008 0.007 0.024 0.008 0.008 0.030 0.011 0 - 0 2 - 0 3 - 0 1 - notes : 1. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm. seating plane e b 4x 4x 64 1 17 32 33 48 49 gage plane r1 r2 0.25mm s l 0 3 - 0 2 - h e e1 e2 a a b d c aaa b a d h bbb ddd m c b a s s d b d1 d2 d d a a2 a1 0.05 s l1 c 0 1 - 0 - c c ccc GL811E aaaaaaagaa ywwxxxxxxxx date code lot code internal no. code no. green package figure 7. 3 - GL811E 64 pin lqfp package
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 34 16 control dimensions are in millimeters. symbol millimeter inch min. nom. max. max. min. nom. a a1 a2 d d1 e e1 r2 r1 c l l1 s b e aaa bbb ccc ddd d2 e2 tolerances of form and position 12.00 basic 12.00 basic 10.00 basic 10.00 basic 0.472 basic 0.472 basic 0.393 basic 0.393 basic 0.05 0.95 1.00 1.20 0.15 1.05 0 0 11 11 3.5 12 12 7 13 13 0.08 0.08 0.20 0.003 0.003 0.008 0 0 11 11 3.5 12 12 7 13 13 0.047 0.006 0.041 0.039 0.002 0.037 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.50 basic 7.50 basic 7.50 basic 0.020 basic 0.295 basic 0.295 basic 1.00 ref 0.039 ref 0.09 0.45 0.20 0.17 0.60 0.20 0.20 0.75 0.27 0.004 0.018 0.008 0.007 0.024 0.008 0.008 0.030 0.011 0 - 0 2 - 0 3 - 0 1 - notes : 1. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm. seating plane e b 4x 4x 64 1 17 32 33 48 49 gage plane r1 r2 0.25mm s l 0 3 - 0 2 - h e e1 e2 a a b d c aaa b a d h bbb ddd m c b a s s d b d1 d2 d d a a2 a1 0.05 s l1 c 0 1 - 0 - c c ccc GL811E aaaaaaagaa ywwxxxxxxxx date code lot code internal no. code no. green package figure 7. 4 - gl 811e 64 pin t qfp package
GL811E usb 2.0 to ata/atapi bridge controller ?2000 - 200 4 genesys logic inc. - all rights reserved. page 35 chapter 8 ordering information table 8.1 - ordering information part number package status 48 - pin lqfp 64 - pin lqfp 48 - pin tqfp GL811E 64 - pin tqfp

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